Yamaha DX7 chip reverse-engineering, segment 4: how algorithms are implemented

Yamaha DX7 chip reverse-engineering, segment 4: how algorithms are implemented

The Yamaha DX7 digital synthesizer (1983) changed into once the classic synthesizer in 1980s pop music.
It makes utilize of two custom digital chips to generate sounds with a scheme called FM synthesis,
producing complex, harmonically-neatly off sounds.
Each and every demonstrate changed into once implemented with one of 32 diverse patterns of modulation and summing, called algorithms.
On this weblog post, I seek right thru the sound chip and indicate how the algorithms had been implemented.

Die photo of the YM21280 chip with the main functional blocks labeled. Click this photo (or any other) for a larger version.

Die photo of the YM21280 chip with the main purposeful blocks labeled. Click on this photo (or any other) for a bigger model.

The die photo above reveals the DX7’s OPS sound synthesis chip underneath the microscope, showing its complex silicon circuitry.
Now not like unusual chips, this chip has correct one layer of steel, visible as the whitish traces on top.
Across the sides, you might perhaps perhaps presumably seek the 64 bond wires linked to pads; these connect the silicon die to the chip’s 64 pins.
On this weblog post, I’m specializing in the highlighted purposeful blocks: the operator computation circuitry that mixes the oscillators, and the algorithm ROM that defines
the diverse algorithms.
I toddle to define the opposite purposeful blocks temporarily.
Each and every of the 96 oscillators has a segment accumulator used to generate the frequency.
The sine and exponential ideas are implemented with lookup tables in ROMs.
Other purposeful blocks prepare the envelope, retain configuration files, and buffer the output values.

The DX7 changed into once the first commercially a hit digital synthesizer, the usage of a radically new scheme of generating sounds.
Except for the analog oscillators and filters of an analog synthesizer, the DX7 generates sounds digitally, the usage of a scheme called FM synthesis.
The root is that you inaugurate with a sine wave (the provider signal) and perturb it with but one more signal (the modulating signal). The modulating signal adjustments the segment (and thus the frequency) of the provider, increasing complex harmonic structures.
The custom chips right thru the DX7 made this that you might perhaps perhaps presumably trust of at an cheaper stamp.

The DX7 synthesizer. Photo by rockheim (CC BY-NC-SA 2.0).

FM synthesis

I toddle to temporarily indicate how FM synthesis is implemented.1
The DX7 helps 16 simultaneous notes, with 6 operators (oscillators) for each demonstrate, 96 oscillators in total.
Nonetheless, to reduce the hardware requirements, the DX7 handiest has a single digital oscillator circuit.
This circuit calculates each operator for my share, in sequence. Thus, it takes 96 clock cycles to interchange the total sounds.
To retain tune of each oscillator, the DX7 stores 96 segment values, an index into the sine wave desk.
By incrementing the index at a particular charge, a sine wave is produced at the specified frequency.

The root of FM synthesis is to modulate the index into the sine wave desk; by perturbing the index, the output sine wave is modified.
The diagram underneath reveals the consequences of modulation.
The discontinue curve reveals a sine wave, generated by stepping thru the sine wave desk at a mounted charge.
The 2d curve reveals the consequences of a small quantity of modulation, perturbing the index into the desk. This distorts the sine wave, compressing and stretching it.
The third curve reveals the consequences of a colossal quantity of modulation. The index now sweeps serve and forth right thru the total desk, distorting the sine wave unrecognizably.
As you might perhaps perhaps presumably seek, modulation can develop very complex waveforms.
These waveforms like a neatly off harmonic development, yielding the characteristic sound of the DX7.
(I made a webpage right here the put you might perhaps perhaps presumably experiment with the consequences of modulation.)

Modulation examples. The top sine wave is unmodulated. The middle wave has a small amount of modulation. The bottom wave is highly modulated.

Modulation examples. The discontinue sine wave is unmodulated. The center wave has a small quantity of modulation. The backside wave is extremely modulated.


The above share illustrated how two oscillators might perhaps well perhaps well very neatly be mixed with modulation.
The DX7 extends this precept,
generating a demonstrate by combining six oscillators thru modulation and summing.
It implements 32 diverse solutions of combining these oscillators, illustrated underneath, and calls each an algorithm.
The assorted algorithms present flexibility and kind in sound introduction.
Multiple ranges of modulation develop harmonically-neatly off sounds. On the opposite hand, a pair of output operators allow diverse sounds to be mixed.
An electrical piano sound, for instance, might perhaps well perhaps well like one sound for the hammer thud, a 2d sound for the physique of the tone, and a third sound for the ringing tine,
all diverse over time.

The 32 algorithms of the DX7 synthesizer.

The 32 algorithms of the DX7 synthesizer.

Having a concept at algorithm #8, for instance, reveals the pattern of an algorithm.
Each and every field represents an operator (oscillator).
Operators 1 and 3 (in blue), are mixed to design the output.
The final operators present modulation, as indicated by the traces.
Operator 2 modulates operator 1.
Operators 4 and 5 are mixed to modulate operator 3, offering a complex modulation.
Operator 6, in turn, modulates operator 5.
At closing, the twin carriageway looping round operator 4 implies that operator 4 modulates itself.
Since each modulation degree can vary over time, the following sound might perhaps well perhaps well very neatly be very complex.

Algorithm 8 combines the six operators; two produce outputs.

Algorithm 8 combines the six operators; two develop outputs.

Shift-register storage

To treasure the DX7’s architecture, it is crucial to know that
the chip makes utilize of shift registers, quite than RAM, for its storage.
The root is that bits are shifted from stage to stage each clock cycle. When a shrimp bit reaches the cease of the shift register, it’d very neatly be fed serve into the register or
a brand new bit might perhaps well perhaps well very neatly be inserted.
For the segment accumulators, the shift registers are 96 bits long since there are 96 oscillators.
Other circuits utilize 16 bit-shift registers to retain values for the 16 voices.
The shift register circuitry (underneath) is dense, moreover, it takes up a colossal allotment of the chip.

A small part of the shift register storage.

A small segment of the shift register storage.

The usage of shift registers vastly affects the beget of the DX7 chip.
In particular, values can’t be accessed arbitrarily, as in RAM.
As a change, values can handiest be used once they exit the shift register, which makes the circuit beget a ways more constrained.
Furthermore, circuits must be fastidiously designed so that each path of a computation takes an analogous quantity of cycles (e.g. 16 cycles).
Shorter paths must be delayed as compulsory.2

I are attempting to emphasise how recurring this chip is, in contrast to a microprocessor.
That that you might perhaps perhaps well question that an algorithm is implemented with code, for instance finding out operator 2, making utilize of modulation to operator 1, and then storing the consequence in operator 1.
As a change, computation happens repeatedly in the chip, with files going in the circuitry every clock cycle because it comes from the shift registers.
The chip is more love an assembly line with bits repeatedly transferring on many conveyor belts, and circuits progressively working on bits as they switch by.
An salubrious thing about this design is that each clock cycle, calculations occur in parallel in a pair of system of the chip, offering great increased performance than a microprocessor might perhaps well perhaps well in the 1980s.

Implementation of the algorithms

The block diagram underneath reveals the final development of the OPS sound chip.
The root is that the envelope chip (EGS) repeatedly offers frequency (F) and envelope alter (EC) values at the head.
The DX7’s alter CPU updates the algorithm (A) if the patron selects a brand new one.
The sound chip generates digital files (DA) for the 16 voices, which is fed out at the first-charge. (The DX7’s digital-to-analog converter circuitry (DAC) converts these digital
values to the analog sound from the synthesizer.)

Diagram showing the architecture of the OPS chip, from the DX7/9 Service Manual.

In extra aspect, the circuitry in the upper left generates the segment values for the 96 oscillators and appears to be like up the values in the sine wave desk.
In the decrease-left, the highlighted block implements the algorithm, producing two outputs.
This block contains its receive storage: the memory (M) register and feedback (F) register.
It generates a modulation price that modulates the index into the sine wave desk.
It also produces the digital sound price that is the output from the chip.
(This highlighted block is the level of ardour of this article.)
On the first-charge, the CPU specifies the algorithm quantity; the algorithm ROM specifies the algorithm by generating alter alerts COM, SEL, and so forth.

The DX7 has 96 oscillators, which are up to this level in sequence.
The cycle of 96 updates takes screech as shown underneath.
In the first clock cycle, computation starts for operator 6 of dispute (channel) 1.
In the next clock cycles, operator 6 processing starts for voices 2 thru 16.
Next, operator 5 is processed for the 16 voices, and likewise for operators 4 to 1.
On the cease of this cycle, the total notes were up to this level.
Two components are crucial right here.
First, operators are processed “backward”, starting at 6 and ending at 1.
2nd, for a particular dispute, there are 16 clock cycles between successive operators.
This scheme that 16 cycles are on hand to compute each operator.

A complete processing cycle, as shown in the service manual. The overall update rate is 49.096 kHz providing reasonable coverage of the audio spectrum.

A complete processing cycle, as shown in the provider manual. The general change charge is 49.096 kHz offering cheaper coverage of the audio spectrum.

The diagram underneath offers more aspect of highlighted block above, the circuitry that modulates the waveform in preserving with a particular algorithm.
The discontinue of modulation is to perturb the segment attitude old to lookup in the sine wave desk.3
On the backside correct, the signal from operator N+1 enters, and is used to compute the modulation for operator N, exiting at the backside left.

Diagram showing modulation computation, from the patent. Inconveniently, the signal names are inconsistent with the service manual.

Diagram showing modulation computation, from the patent. Inconveniently, the signal names are inconsistent with the provider manual.

The significant aspect is the selector at the left, which selects some of the 5 modulation picks, primarily primarily based on the alter signal S or SEL.
Initiating at the backside of the selector, SEL=1 selects the unmodified signal from the input operator; this implements the easy modulation of an operator by but one more.
Next, SEL=2 makes utilize of the price from the adder (61) for modulation. This permits an operator to be modulated by the sum of operators, for instance in algorithm 7.
SEL=3 makes utilize of the delayed price from the buffer; that is used fully for algorithm 21, the put operator 6 modulates operator 4.
SEL=4 and SEL=5 utilize the self-feedback operator for modulation. Since the feedback price is buffered in the circuitry, it is on hand at any time, not like other operators.
SEL=4 is used to beget delayed feedback, for instance when operator 6 modulates operator 4 in algorithm 19.
(In most cases, feedback is applied immediately, for instance when operator 6 modulates operator 5, and this makes utilize of SEL=1.)
SEL=5 handles the self-feedback case; the old two feedback values are averaged to develop steadiness.4
The SEL=0 case just will not be shown; it causes no modulation to be chosen so the operator is unmodulated.

Several alter alerts (A, B, C, D, E) also alter the circuit.
(Confusingly, the patent diagram underneath makes utilize of the names A and B for the feedback register allow (FREN) line.
The memory register allow (MREN) traces are called C and D.)
Signals A and B just like the same price: they possess out if the feedback buffer continues to retain the old price or loads a brand new price.
Signals C and D alter the buffer/sum shift register.
If C is 1 and D is 0, the register holds its old price. If C is 0 and D is 1, the input signal is loaded into the register.
If each C and D are 1, the input signal is added to the old price.
This register might perhaps well perhaps well very neatly be used to sum two modulation alerts, as in algorithm 7. But it is a ways in overall used to retain and sum the output alerts.
(As a final consequence, an algorithm can’t sum modulation alerts and outputs at the same time.)
Signal E loads the algorithm’s closing output price into the output buffer (70). Signal E and buffer 70 are implemented one at a time, so I could perhaps well perhaps well not discuss them extra.

The algorithm ROM

The algorithms are outlined by a ROM with 9-bit entries that retain the selector price (SEL), the alter alerts MREN and FREN (A,C,D), and the compensation scaling price COM (which I indicate later).
Each and every algorithm desires 6 entries in the ROM to make your mind up the action for the 6 operators.
Thus, the ROM holds 96 9-bit values.

The photo underneath reveals the algorithm ROM. It has 32 columns, one for each algorithm and 9 teams of 6 rows: one personnel for each output bit.
From backside to top, the outputs are three bits for the selector price SEL, two MREN traces and the FREN line, and three bits for the COM price.
The teams of 6 diagonal transistors at the left of the ROM possess out the entry for the contemporary operator.

The algorithm ROM. The metal layer has been removed to show the silicon structure underneath that defines the bits.

The algorithm ROM. The steel layer has been eradicated to level the silicon development underneath that defines the bits.

The bits are visible in the sample of the ROM. By inspecting the ROM closely, I extracted the ROM files. Each and every entry is formatted as “SEL / A,C,D / COM”. (I handiest indicate three entries underneath; the beefy ROM is in the footnotes.5)

Algorithm 6 5 4 3 2 1
1 1/100/0 1/000/0 1/000/1 0/001/0 1/010/1 5/011/0
2 1/000/0 1/000/0 1/000/1 5/001/0 1/110/1 0/011/0
8 1/000/0 5/001/0 2/111/1 0/001/0 1/010/1 0/011/0

To seek how an algorithm is implemented, clutch into consideration operator 8, for instance.6

Algorithm 8 has four modulators and two carriers.

Algorithm 8 has four modulators and two carriers.

Processing of an algorithm starts with
operator 6’s signal price at the output of the operator block and operator 5’s modulation is being computed.
Desk column 6 above reveals SEL=1, A,C,D=000.
In the modulation circuit (underneath), SEL=1 selects the raw signal in (i.e. operator 6’s price) for modulation.
Thus, operator 6 modulates operator 5, the specified behavior for algorithm 8.

Diagram showing modulation computation.

Diagram showing modulation computation.

Next, (16 cycles later), operator 5’s signal is at the output and operator 4’s modulation is being computed.
Column 5 of the desk reveals SEL=5, A,C,D=001.
SEL=5 selects the filtered feedback register for self-modulation of operator 4.
D=1 causes operator 5’s price to be loaded into the shift register, in preparation for modulating operator 3.

Next, operator 4’s signal is at the output and operator 3’s modulation is being computed.
Column 4 reveals SEL=2 and A,C,D=111.
Bits A (and B) are 1 to load the feedback register with operator 4’s price, updating the self-feedback for operator 4.
Bits C and D trigger operator 4 to be added to the previously-saved operator 5 price.
SEL=2 selects this sum for operator 3’s modulation, so operator 3 is modulated by each operators 4 and 5.
COM=1 signifies this operator is one of two outputs, so operator 3’s price will be divided by 2 because it is computed.

Next, operator 3’s signal is at the output and operator 2’s modulation is being computed.
Having a concept at the ROM, SEL=0 ends in no modulation of operator 2.
D=1 loads operator 3’s signal into the summing shift register, in preparation for the output.

Next, operator 2’s signal is at the output and operator 1’s modulation is being computed.
SEL=1 causes operator 1 to be modulated by operator 2.
C=1 so the summing shift register continues to retain the operator 3 price, to develop the output.
As with operator 3, COM=1 so operator 1’s price will be divided by 2 when it is computed.

At closing, operator 1’s signal is at the output and operator 6’s modulation is being computed.
SEL=0 signifies no modulation of operator 6.
Adjust alerts C and D are 1 so operator 1 is added to the register (which holds operator 3’s price), forming the closing output.

This job repeats cyclically, interleaved with processing for the 15 other voices.
This share illustrates how a complex algorithm is implemented thru the modulator circuitry, directed by about a alter alerts from the ROM.
The opposite algorithms are implemented in identical solutions.7

The modulation circuitry

The diagram underneath reveals the circuitry that computes the modulation and output; this purposeful block is in the heart of the chip.
The memory register (red) holds 16 values, one for each dispute. To its correct, the adder (blue) provides to the price in the memory register.
The selector (crimson), is the center of the circuit, deciding on which price is used for modulation.
It is managed by the selector decoder (orange) at the backside, which prompts a alter line primarily primarily based on the three-bit SEL price.
On the a ways correct, the two feedback registers (red) retain the closing two feedback values for each of the 16 voices.
The feedback adder sums two feedback values to beget the moderate.
The feedback shifter (yellow) scales the feedback price by a energy of two.

The circuitry that calculates the modulation for the algorithm.

The circuitry that calculates the modulation for the algorithm.

Shift registers

The schematic underneath reveals how one stage of the shift register is implemented.
The chip makes utilize of a two-segment clock.
In the first segment, clock ϕ1 goes excessive, turning on the first transistor.
The input signal goes thru the inverter, thru the transistor, and the voltage is saved in the capacitor.
In the 2d segment, clock ϕ2 goes excessive, turning on the 2d transistor.
The price saved in the capacitor goes thru the 2d inverter, thru the 2d transistor, and to the output, the put it enters the next shift register stage.
Thus, in one clock cycle (ϕ1 and then ϕ2), the input bit is transferred to the output.
(The circuit is the same to dynamic RAM in the sense that bits are saved in capacitors.
The clock desires to cycle old to the charge on the capacitor drains away and files is misplaced.
The inverters elevate and regenerate the bit at each stage.)

Schematic of one stage of the shift register.register.” width=”450″>

Schematic of one stage of the shift register.

The diagram underneath reveals segment of the shift register circuitry because it appears to be like on the die.
The blue rectangle signifies one shift register stage.
The energy, ground, and clock wiring is in the steel layer, which changed into once largely eradicated on this image.
Shift register phases are linked horizontally.
Shift registers for separate bits are stacked vertically, with alternating rows mirrored.

Die photo showing a stage of the shift register.register.” width=”400″>

Die photo showing a stage of the shift register.

The selector

The selector circuit selects some of the 5 doable multiplexer values, primarily primarily based on the SEL input.
The circuit makes utilize of 5 toddle transistors (indicated in yellow) that toddle some of the 5 inputs to the motive force circuit and then the output.
(A sixth transistor pulls the output excessive if not some of the inputs is chosen; I’ve labeled this “x”.)
The diagram underneath reveals one selector in the head half of, and a replicate-image selector underneath; there are 12 selector circuits in total.
The circuit is constructed round the six vertical possess out traces.
One possess out line is activated to make your mind up a particular price. This turns on the corresponding transistors, allowing that input to waft thru the transistors.
The cease consequence goes thru but one more transistor to synchronize it to the clock, and then an inverter/buffer to drive the output line.
The outputs toddle to the sine-wave circuit, the put they modulate the input to the lookup desk.

Two stages of the selector.

Two phases of the selector.

The adder

The chip contains a pair of adders. Two adders are utilized in the modulation computation: one to sum operators and one to moderate the two old feedback values.
The adders are implemented with a conventional binary circuit called a beefy adder.
A beefy adder takes two input bits and a raise-in bit. It provides these bits to generate a sum bit and a raise-out bit.
By combining beefy adders, larger binary numbers might perhaps well perhaps well very neatly be added.

Diagram showing a full adder.

Diagram showing a beefy adder.

The diagram above reveals a beefy adder stage in the chip. The circuit is constructed from three fairly complex gates, nonetheless whereas you are attempting the diverse input combos, you
can seek that produces the sum and lift.
(Because of the properties of NMOS circuits, it is more efficient to utilize a small quantity of complex gates quite than a bigger quantity of easy gates equivalent to NAND gates.)

One screech of affairs with binary addition is that it’d very neatly be fairly slack for carries to propagate thru the total phases. (Right here’s the binary identical of 99999 + 1.)
The answer utilized in the DX7 is pipelining: an addition operation is destroy up right thru a pair of clock cycles, quite than being done in a single clock cycle.
This reduces the quantity of carries in one clock cycle.
Even though a particular addition takes plenty of clock cycles, the adders are saved busy with other additions, so one addition is done every cycle.

The compensation (COM) computation

In the DX7, diverse algorithms like diverse numbers of oscillators in the output, which poses a screech of affairs
An algorithm with 6 output oscillators (e.g. #32) might perhaps well perhaps be six instances as loud as an algorithm with 1 oscillator (e.g. #16), which might perhaps well perhaps be traumatic as the patron adjustments the algorithm.
To manual clear of this screech of affairs, the chip scales the degree of output oscillators accordingly. As an illustration, the ranges of output oscillators in algorithm #32
are scaled by 1/6 to even out the volumes.
This aspect is known as COM (compensation) in the provider manual and ADN (addition channel quantity) in the patent.8
To place into effect this scaling, the algorithm ROM holds the output depend for each operator, minus 1.
As an illustration, algorithm #32 has six output oscillators, each having a COM price of 5 (i.e. 6-1).
For algorithm #1, the two output oscillators are 1 and 3: these like a COM price of 1 (i.e. 2-1).
Operators that are used for modulation are not scaled, and like a COM price of 0.

Opt that the envelope scaling is done by adding irascible-2 logarithms. The COM scaling also makes utilize of logarithms, which are subtracted to scale down the output degree.
A small ROM generates 6-bit logarithms for the COM values 1 thru 5, identical to scale components 2 thru 6.
The diagram underneath reveals the COM circuitry, which is in the upper-correct corner of the chip.
On the left, the decoder and little ROM resolve the logarithmic scaling aspect from the quantity of inputs.
Right here’s added to the logarithmic envelope degree that the chip receives from the envelope chip.
The cease consequence goes thru about a shift register phases for timing reasons.

The COM circuitry adds a compensation level to the envelope to compensate for algorithms with multiple outputs.

The COM circuitry provides a compensation degree to the envelope to catch up on algorithms with a pair of outputs.


The DX7’s algorithm implementation circuitry is at the center of the chip’s sound technology.
This circuitry is cleverly designed to put into effect 32 diverse algorithms at excessive tempo with the restricted hardware of the 1980s.
The circuitry runs fleet ample to job 16 voices sequentially, each with 6 separate oscillators, whereas producing outputs fleet ample to develop audio alerts.
By taking salubrious thing regarding the pipelined architecture constructed round shift registers, the chip processes a diverse oscillator right thru each clock cycle, a excellent throughput.
Overall, I’m impressed with the beget of this chip.
Its reducing-edge beget changed into once the main to the DX7’s capacity to develop dramatic new sounds at a low stamp.
Which skill, the DX7 outlined the canonical sound of the 1980s and changed the route of pop music.

I design to proceed investigating the DX7’s circuitry,
so apply me on Twitter @kenshirriff for updates. I also like an RSS feed.
Additionally seek my old posts on the DX7:
DX7 reverse-engineering,
the exponential ROM,
The log-sine ROM.

Thanks to Jacques Mattheij and Anthony Richardson for offering the chip and discussion.9

Notes and references



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