Yamaha DX7 chip reverse-engineering, part V: the output circuitry

Yamaha DX7 chip reverse-engineering, part V: the output circuitry

The Yamaha DX7 digital synthesizer (1983) became the conventional synthesizer in 1980s pop music.
It uses a methodology known as FM synthesis to
originate complex, harmonically-prosperous sounds.
On this blog post, I gape interior its custom sound chip and present how the chip’s output circuitry works.
It is probably you’ll per chance build a query to it is lawful a digital output fed correct into a digital-to-analog converter, but there might be great extra to it than lawful that.

Die photo of the YM21280 chip with the main functional blocks labeled. Click this photo (or any other) for a larger version.

Die picture of the YM21280 chip with the vital practical blocks labeled. Click on this picture (or any assorted) for an even bigger model.

The composite die picture above reveals the DX7’s OPS sound synthesis chip below the microscope, revealing its complex silicon circuitry.
Not like contemporary chips, this chip has lawful one layer of metallic, viewed as the whitish strains on top.
Around the perimeters are the 64 bond wires connected to pads; these join the silicon die to the chip’s 64 pins.
The three blocks in red are the purpose of curiosity of this post.
The output buffers preserve the 16-bit digital values for the 16 notes.
The output is controlled by a counter and PLA (Programmable Good judgment Array).
The synthesizer’s digital-to-analog conversion uses a pattern-and-preserve circuit, controlled by the “S/H ctrl” block.

I’ve talked about the chip’s assorted practical blocks in earlier posts1, so I’m going to lawful give a transient abstract right here.
Each of the 96 oscillators has a part accumulator outmoded to generate the frequency.
The oscillators are blended using the operator computation circuitry within the guts of the chip, below the retain watch over of the algorithm ROM.
The signal synthesis uses sine and exponential functions, implemented with search for tables in ROMs.

The Yamaha DX7 synthesizer with its 61-key keyboard and digital controls. Photo by rockheim (CC BY-NC-SA 2.0).

The Yamaha DX7 synthesizer with its 61-key keyboard and digital controls. Report by rockheim (CC BY-NC-SA 2.0).

The synthesizer’s output circuitry

Before I dive into the crucial parts of the chip, I’m going to present the synthesizer’s output circuit.
The coronary heart of the synthesizer is the OPS (Operator S) sound chip that digitally generates the notes.
It gives digital values to the digital-to-analog converter (D/A). The following analog signal goes thru a low-cross filter (LPF).
The volume is controlled by a foot pedal and the synthesizer’s volume retain watch over.
At last, the signal is amplified for the line and headphone outputs.

Block diagram of the output circuit. Based on the DX7/9 Service Manual.

The digital-to-analog conversion is extra complex than you might build a query to.
The approach begins with the digital-to-analog converter (DAC) chip2
that takes a 12-bit digital rate from the sound chip and converts it to an analog rate
within the fluctuate 0 to 15 volts.3
The multiplexer permits the total synthesizer volume to be controlled by MIDI, but with lawful 8 ranges.

Schematic of the volume control and DAC circuit. Based on the DX7 schematics.

Schematic of the quantity retain watch over and DAC circuit. Essentially based on the DX7 schematics.

The DAC gives 12 bits of resolution, but an further circuit (below) gives approximately two extra bits.
This scaler circuit divides the analog signal by 1, 2, 4, or 8, using a resistor community and IC switch.
The scaler is controlled by the sound chip thru the scale part indicators SF0-SF3.
The scaler provides extra dynamic fluctuate to the digital rate; the fruits’s much like a floating-point rate with a label bit, 11-bit mantissa, and two-bit exponent.4

The scaler divides the voltage by 1, 2, 4, or 8. Based on the DX7 schematics.

The scaler divides the voltage by 1, 2, 4, or 8. Essentially based on the DX7 schematics.

Next, the signal goes to a pattern-and-preserve circuit that samples the analog voltage at a degree in time and holds it in a capacitor,
extra or much less love an analog memory. An op-amp buffers the capacitor’s voltage so it’ll be “learn” without draining the capacitor.
There are two preserve circuits, outmoded in alternation, so the last two samples are kept and summed
to construct the circuit’s output.5
The SH1 and SH2 retain watch over indicators load the analog rate correct into a capacitor, using IC52 as a switch.
At last, the output from the pattern-and-preserve circuit is filtered,6 the quantity is adjusted,7 and the signal is amplified for the output (circuitry no longer confirmed).

The sample-and-hold circuit. IC52 looks complicated because it uses pairs of switches in parallel. Based on the DX7 schematics.

The pattern-and-preserve circuit. IC52 appears refined because it uses pairs of switches in parallel. Essentially based on the DX7 schematics.

To summarize, the sound chip interacts with the output circuitry in three solutions.
The 12-bit digital rate (DA1-DA12) is important because it specifies the output rate for every hiss.
The scale part indicators (SF0-SF3) are moreover a key contributor to the signal.
The sound chip moreover gives the pattern-and-preserve retain watch over indicators (SH1 and SH2).

Time-division multiplexing

The DX7 has 16 voices, so it’ll play 16 notes straight away.
Each point out is produced by an “algorithm” that mixes 6 oscillators in a particular manner, so there are 96 oscillators in total.
An oscillator can modulate the frequency of 1 other oscillator to generate complex sounds with FM synthesis.

The chip performs all its processing sequentially, one oscillator at a time, as an alternative of computing the notes in parallel.
Internally, the chip has one “operator” calculation circuit to combine oscillators.
As confirmed below, the chip begins by processing operator 6 for point out 1, then operator 6 for point out 2, and so forth thru point out 16.
Then it processes operator 5 for notes 1 thru 16.
At last it processes operator 1 for notes 1 thru 16, producing the output sound values.
It takes a small over 20 µs to compute all 16 notes in a total processing cycle.

Timing diagram of sound production. This time interval corresponds to 49.096 kHz. From the DX7/9 Service Manual.

Timing plot of sound manufacturing. This time interval corresponds to 49.096 kHz. From the DX7/9 Service Manual.

It is probably you’ll per chance build a query to the chip to combine the 16 notes correct into a single digital output.
the sound chip outputs the 16 notes sequentially,
using a methodology known as time-division multiplexing.
Every time interval (~20µs) is split into 16 intervals and one point out is output from the chip per interval.
(Suppose that these intervals originate no longer line up with the intervals within the plot above.)
Thus, digital values are output at 786 kilohertz, 16 cases the underlying frequency, and the DAC chip converts them to analog at this fee.

As an illustration, have in solutions two notes that are sine waves with assorted frequencies.
The digital output would gape love the image below.
It is probably you’ll per chance contemplate that this signal is unusable because it jumps round wildly from impress point.

Output data with two multiplexed sine waves. (Theoretical, not actual DX7 data.)

Output knowledge with two multiplexed sine waves. (Theoretical, no longer exact DX7 knowledge.)

Nonetheless, making spend of a low-cross filter smooths out the waveform (in actual fact summing nearby parts).
The fruits’s the waveform below, which reveals the sum of the 2 sine waves.8
The purpose is that time-division multiplexing knowledge might well gape unfamiliar, however the analog circuitry’s filtering creates
a “traditional” waveform.

Output data after filtering with a 16 kHz low-pass filter.

Output knowledge after filtering with a 16 kHz low-cross filter.

Output buffer

Interior the chip, the output buffer stores values for the 16 notes as they are generated, and outputs them in sequence.
In negate of RAM, the chip uses shift registers for storage.
The shift registers are organized in a loop of 16 phases, one stage for every point out.
On every clock cycle, the values within the shift register transfer to the following stage.
The output rate is fed abet into the shift register’s enter so the rate is retained.
Alternatively, a recent rate would per chance be kept within the shift register.
Shift registers equipped an atmosphere effective manner to retailer knowledge, but they might be able to’t be accessed arbitrarily;
as an alternative, knowledge might well restful be processed because it becomes on hand.

The schematic below reveals how one stage of the shift register is implemented.
The chip uses a two-part clock.
Within the first part, clock ϕ1 goes excessive, turning on the first transistor.
The enter signal goes thru the inverter, thru the transistor, and the voltage is kept within the capacitor (extra or much less love DRAM).
Within the 2nd part, clock ϕ2 goes excessive, turning on the 2nd transistor.
The rate kept within the capacitor goes thru the 2nd inverter, thru the 2nd transistor, and to the output, where it enters the following shift register stage.

Schematic of one stage of the shift register.

Schematic of 1 stage of the shift register.

The die picture below reveals the output buffer, with the 16 shift-register loops organized in columns.
These preserve the 16-bit sound values (four scale part bits and 16 knowledge bits.)
Each shift register is 16 phases prolonged to preserve up the 16 notes.
Within the following sections, I’m going to chat about the bit shifters, the good judgment, and the output latches.

Closeup of the die, showing the output buffer circuitry.

Closeup of the die, showing the output buffer circuitry.

The scale part: pseudo floating point

The DX7 uses a 12-bit digital-to-analog converter chip, however the scaling circuit (talked about earlier) will scale the voltage by 1, 2, 4, or 8, which provides extra resolution.
This is now not any longer barely much like 14-bit resolution; it is extra love a floating-point quantity with a label, 11-bit mantissa, and a pair of-bit exponent.
This gives extra resolution for low indicators and reduces signal noise.

Interior the chip, scaling is implemented with a shifter that shifts the guidelines bits by 0 to three bit positions.
(Here’s unrelated to the shift registers that preserve knowledge.)
The shifter (below) is implemented as eleven chevron-shaped good judgment gates; every gate selects definitely one of four doable bits for every mantissa negate.

A data sample is shifted 0 to 4 bits by this shifter circuit.

A knowledge pattern is shifted 0 to 4 bits by this shifter circuit.

The operator circuitry generates knowledge as 15 bits (2’s complement, so definitely one of the vital bits gives the label).
The output from the chip is 12 bits, so three bits might well restful be discarded.
Typically these are the low-roar bits, but by utilizing the shifter, excessive-roar zero bits would per chance be discarded as an alternative, and the originate air scaler counteracts this.
The fruits’s extra bits of precision within the output.

The shifter is controlled by the good judgment circuitry to the left of the buffer, which controls the amount of shift in accordance to the
different of leading zeros. (For a detrimental quantity, leading 1’s.)
With 5 leading zeros, the quantity is shifted left by 3 positions.
With 4 leading zeros, the quantity is shifted by 2 positions.
With 3 leading zeros, the quantity is shifted by 1 negate.
With 2 or fewer leading zeros, the quantity is unshifted.

Suppose that the circuit leaves two leading zeros when it shifts, so it is “wasting” two doable bits of precision.
I rob right here’s for the reason that scaler might well no longer be perfectly linear (attributable to the resistor imperfections9), so you might per chance must steer definite of switching
scale ranges for gargantuan indicators (which originate no longer in actual fact select the further bits).10

The output latches

As talked about earlier, the 16 notes are output for my fraction, spaced across the interval.
This timing would now not line up with the timing of the output buffer, which shifts to a recent point out every clock cycle.
To repair the timing, two 16-bit latches take a seat between the output buffer and the output pins.
Whereas one latch outputs the recent point out, the assorted latch grabs the following point out because it is shifted out of the shift register.
On the appropriate time, the latches swap roles; the 2nd latch outputs the purpose out while the first latch waits for the following point out.

The timing for the latches is barely refined to create obvious the purpose out knowledge is loaded into the factual latch on the factual time.
These latches are controlled by the chip’s master counter, which is the field of the following part.

To summarize, the sound chip runs at 4.7 MHz. Files values are produced at this fee (but intermittently) and kept
into the output buffer. The output latches present knowledge values to the DAC chip at 786 kHz for an total audio fee of 49096 kHz.

Conserving display screen of 96 clock cycles: the chip’s counter and timing PLA

One total cycle of the sound chip takes 96 clock cycles: processing all 16 notes thru the 6 operators that build an algorithm.
Because knowledge can simplest be accessed when it exits a shift register, every little thing might well restful be timed so the factual knowledge is on hand on the factual time.
A vital a part of the chip is the counter that retains display screen of the recent point out quantity and operator quantity to retain every little thing

On the factual of the die picture below is the counter, consisting of seven toggle flip flops: four to count the purpose out quantity (0-15) and three to count the algorithm quantity (0-5).
On the left is the PLA that defines what occurs for particular time slices.
(A Programmable Good judgment Array (PLA) is much like a ROM, but implements arbitrary good judgment.)
The PLA has 39 columns, every body imposing an AND gate triggered by a particular counter output, much like a particular operator and point out.
Below the PLA is a pair of good judgment; largely buffers with a pair of gates.

The chip's main counter, along with the control PLA.

The chip’s vital counter, along with the retain watch over PLA.

Of the PLA’s 39 columns,
the 32 columns on the left retain watch over the guidelines output latches,11
two columns retain watch over loading knowledge values into the output buffer,
one generates the chip’s sync output signal,
three reset the operator count,
and the last increments the operator count.12


The chip outputs two indicators to retain watch over the pattern-and-preserve circuitry, SH1 and SH2. These indicators are activated in alternation
to consume an analog pattern of every digital output.

The sound chip on the DX7 schematic has three missing pins, indicated in red.

The sound chip on the DX7 schematic has three missing pins, indicated in red.

The sound chip has three unused pins next to the SH1 and SH2 pins; the DX7 schematic would now not point out pins 6-8. I traced the chip’s interior circuitry and came across that these pins, along with the pattern-and-preserve pins,
count out the 16 samples.
It seems that the chip is designed to pattern-and-preserve all 16 notes for my fraction, so the synthesizer can have had separate outputs for all 16 notes.13

Moreover, the chip has knowledge buffers to preserve up separate algorithm algorithms for the 16 notes. This would let the chip drive 16 neutral voices, every with a separate algorithm.
My conclusion is that the sound chip helps great extra flexibility than is outmoded within the DX7 synthesizer.


The DX7 generates sounds digitally after which converts the digital values to the analog output.
This route of appears extra refined than one would build a query to, with circuitry within the chip interacting with synthesizer circuitry to scale and alter
the signal.
My hope is that my diagnosis of this route of will benefit DX7 emulators to total extra accuracy.
Having a gape on the chip’s interior circuitry reveals the floating-point format of the output knowledge as properly as the characteristic of
the three unused pins.

I belief to continue investigating the DX7’s circuitry,
so educate me on Twitter @kenshirriff for updates. I moreover have an RSS feed.
Thanks to Jacques Mattheij and Anthony Richardson for providing the chip and discussion.14

Notes and references

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