Sing HN: Verik, a unique language for RTL accumulate and verification

Sing HN: Verik, a unique language for RTL accumulate and verification

Meet this mountainous module!

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Verik is a hardware description language (HDL) for designing and verifying digital integrated circuits.
The purpose of Verik is to enable the stylish IDE workflow to bridge the technology gap between hardware and kit
Verik goals to be an interoperable fall-in replacement for SystemVerilog that leverages the stylish tool stack to
toughen productiveness.
Verik builds upon Kotlin, a unique current-purpose programming language with a perfect and
expressive syntax.
Verik is Kotlin reinterpreted with the semantics of an HDL.
It would possibly per chance well in reality well presumably without delay make exercise of instruments constructed for the vivid Kotlin ecosystem, such as the broadly broken-down
IntelliJ IDEA IDE.

The Verik toolchain consists of two substances, the compiler and the importer.
It serves to bridge the gap between the Kotlin and SystemVerilog environments.
Verik is translated to SystemVerilog by the compiler.
Conversely, SystemVerilog declarations can even even be imported into the Kotlin atmosphere with the importer.
This enable us to make exercise of SystemVerilog libraries such as the UVM
without delay in Verik.
It also reduces the boundaries to adoption by allowing a aggregate of Verik and SystemVerilog to coexist within the same code spoiled.
Customers are in a location to without delay possess the relieve of the productiveness gains of Verik with out having to impress out unique
infrastructure from the bottom Up.


Verik is designed with the
Thought of Least Astonishment in tips.
Most language ideas such as applications, classes, and capabilities are carried over without delay from Kotlin.
As such, the Kotlin documentation is an efficient birth line
for working out Verik.


An instance of a Verik adder module, alongside with the generated SystemVerilog, is confirmed below.
The interpretation is roar, on the total with one-to-one correspondence between the input and output source facts.
The names of declarations are preserved by the translation route of.
Verik generates readable SystemVerilog such as what an engineer would possess written.

Verik Adder

class Adder(
@In var clk: Boolean,
@In var a: Ubit,
@In var b: Ubit,
@Out var x: Ubit
) : Module() {

enjoyable seq() {
on(posedge(clk)) {
x=a + b

SystemVerilog Adder

module Adder(
input logic clk,
input logic [7:0] a,
input logic [7:0] b,
output logic [7:0] x,

always_ff @(posedge clk) open : seq

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